PCB Layout Workflow

Our workflow is standardized across all projects. This uniform approach promotes consistent, predictable results and a low error rate.  PCB layout proceeds along a series of sequential tasks, each one building on the preceding steps.  Although layout projects vary widely in size and scope, the basic workflow applies to all types.  To understand the degree of project completion at checkpoints, or to access the impact of design-time changes, a clear picture of the workflow is necessary.  Our basic workflow diagram is available for viewing or download in PDF format.  Below are detailed descriptions of each task.  The time required to complete each task is dependent on the size, type, and complexity of the project.

Customer Inputs

All PCB layouts begin with specification documents received from engineering.  These standard documents are the board outline drawing, the bill of materials (bom), the circuit schematic, the netlist, and the layout instructions, all described in detail on the Inputs Page.  During the quotation phase, the input documents are reviewed for general completeness and consistency. Where problems are found, details are reported to the document owner for resolution.  Once the project is booked and scheduled, a more thorough review is done as data is prepared for the layout.

Drawing Templates

The format of documentation drawings includes a title block which contains information pertinent to the document's origin, approvals, and revisions.  The format used for fabrication and assembly drawings is for the most part standardized, with minor variations according to the source.  By default, we use our in-house drawing format for all drawings.   We can also provide drawings on custom company title blocks, if a suitable template file is available.

The Layout Footprint Library

Components used in electronic assemblies have three important properties- a manufacturer's part number, a package style, and a corresponding mounting pattern, the "footprint".  Considering the vast number of available parts, and the large and growing number of unique package styles, layout designers use an indexed library system to store and retrieve parts for layout use.   Libraries of parts can be purchased, or created in-house using graphical editors.   In either case, the source of the part package data is always a manufacturer's component datasheet.  Correct footprint patterns are best created from component package dimensions with the help of specialized footprint or "land pattern" calculators.   These calculators produce footprints compliant with IPC-7351B "Generic Requirements for Surface Mount Design and Land Pattern Standard". Libraries allow us to leverage prior research and drawing effort across all layout projects.  While a footprint library could be nothing more than an indexed collection of named footprints,  this type of library can be improved.  A far better library is a list of manufacturer part numbers, with each part number pointing to a particular named footprint stored in a supporting footprint library.  This type of library structure provides major efficiencies over the simpler version. Once a part number and footprint are stored in the library, a call to the library with that partnumber will deliver the correct footprint into the layout without any need to refer to the datasheet. This is the type library we use.

IPC Standards

We design boards using acceptable layout practices as detailed in the  IPC-2200 series of design standards. Additional standards are used for specific applications: IPC-2251(high-speed signaling), IPC-2252 (microwave), and IPC-2152 (conductor current capacity) are a few examples.  Published and maintained by the IPC, these standards provide design guidance for improved electrical performance, manufacturability, and reliability.  While compliance with IPC layout standards is neither mandated nor regulated, competent layout designers refer to IPC publications for acceptable practices.  Adherence to the accepted standards leads to improved quality of electronic assemblies, and can easily reduce production costs by maximizing process yields.

New Board Layouts vs Layout Revisions

The workflow detailed below assumes a new board layout, started from scratch.  New board designs can be a large percentage of a layout designer's work load.  However, the typical workload of a layout department will include the revision of existing designs.  The workflow of revision projects follows the same sequence as new-board design, although the entry point will likely be at some point mid-stream rather than at the  beginning of the flow diagram.  Revisions don't usually change everything on a board, so the work required in each phase will be limited to those board elements and regions in need of change.  We routinely perform board updates for layouts we designed and for boards designed elsewhere.  We maintain an indexed archive for fast retrieval of our prior layouts, and we can import CAD databases from several vendor formats.

New Board Setup

New board projects begin with a selection of an appropriate starting template.  The drawing size we choose will be appropriate to the size of the board.  We maintain templates for all common drawing sizes, and can accommodate custom title blocks when required.  Since fabrication drawings and assembly drawings typically contain a mix of common "boilerplate" and board-specific notes, the templates contain the common notes as a starting point.  The title blocks are written to add the project part numbers, dates, and revision levels.  The board stackup details may not yet be fully known, so we begin by initializing a 2-layer or 4-layer stackup graphic.  At this point, some basic design rules are entered.  Nets are segregated into classes to ease the  management of trace widths & spacings, layer assignments, and high-speed rules.  Initial values are established for trace widths & clearances.

Mechanical Layout

Board layout begins with the entry of a dimensioned board perimeter and any internal cutouts.  This data is taken from the board outline drawing.  Board dimensions entered now will appear later on the fabrication drawing.  Keep-out zones and component height-restricted zones are created, if applicable.  The board thickness is set, and grid increments are defined for component placement, trace routing, and test points.

Netlist Preparation

The netlist file carries component data and connections data from the schematic to the layout system.  Most schematic-capture tools can export netlists targeted to a variety of layout platforms.   The PADS™ netlist format which we use is very common and widely supported.  Provided the schematic tool can output a netlist in the required format, that netlist can be used as direct input to layout. 

Netlist Structure and Format

The structure of a PADS netlist contains two distinct sections.  The first section lists all parts on the circuit schematic. The second section lists the electrical connections.  An example illustrates the two-section format.  In the parts section are two columns- first, reference designator, and second, part description.  With a few exceptions, the description column should contain only manufacturer's part numbers.  The export of part numbers to the netlist is enabled by appropriate settings in the schematic tool. These part numbers will be used by the layout system to retrieve correct footprints for each part. Occasionally, netlists arrive with unusable data in the description column:  Component values, casually-named footprints, and truncated part numbers are typical.  To make the netlist usable for layout input, we must extract part numbers from the BOM and insert these into the netlist.

Netlist/BOM Alignment

To correct faulty part-description fields on a netlist, we use a utility which extracts part numbers from the BOM and inserts those part numbers into the netlist based on the reference designators as a primary key.  We refer to this process as netlist/BOM alignment.  During alignment, certain non-electrical "parts" will also be added to the netlist.  Mounting holes and fiducial (alignment) targets are the most common additions.  While these items are not true "parts", they do need a footprint on the board, and these footprints are most conveniently stored, indexed, and retrieved using the part library.  Occasionally a discrepancy will be noted between the reference designators on the netlist and those on the BOM.  A part may be listed on one document but not on the other, or we may find duplicate reference designators.  Discrepancies of this type are passed to the document owner for resolution.

Netlist Connectivity Section

The netlist connections section contains lists of electrical nodes in the format "refdes-dot-pinnumber". A component reference designator and pin number are separated by a period (dot) character to indicate an electrical node.  Each list of nodes may occupy one line or multiple lines, and is always preceded by a *SIGNAL* net-name line.  Each list of nodes represents a unique net named by the *SIGNAL* line.  A net is a string of interconnected nodes (pins). The order of nodes in a netlist net does not imply any order of connectivity; this order is established during layout. The connectivity section of netlists should always be examined to uncover common errors and format problems.  The most common of these are:

• Device powers or grounds missing. 
• Power or ground nets fragmented. 
• Signal nets fragmented. 
• Casually-named device pins. 
• Inconsistent pinning conventions.
• Incorrect pinning conventions. 

For more details, see "Common netlist errors" in the resources section.

Importing the Netlist

The netlist is imported to the layout system to create a working layout database.  During import, the netlist is parsed to extract part reference designators and part numbers.  For each reference designator, the part number is matched to an entry in the library and the corresponding layout footprint is loaded and drawn to the display.  When all parts have been loaded, the connection nets are loaded and a "rat's nest" of connection lines is displayed.  At this point the parts are in an unorganized pile, outside the board outline.

Placing Fixed Location Parts

Using dimensions found on the board outline drawing, all fixed-location parts are positioned and locked to prevent accidental movement.  The most common examples of fixed-location parts are "user interface" parts:  LEDs, connectors, and switches, items which must mate precisely with holes and cutouts in the enclosure.  In addition to these conventional parts, the board mounting holes and fiducial alignment targets are also installed and locked.  It is customary and good practice to move the layout origin point (0,0) to one of the fiducial targets. Positioning of circuit components and test points will be on grids referenced to this origin.  Downstream assembly will use the fiducial targets and machine vision to achieve precise component positioning .

Pre-Placement Setup

Power Distribution

Before assembling the circuit blocks onto the board, decisions are made concerning power/ground distribution.  Will this be implemented with traces, or planes, or a mix of both?  How many nets are involved? How large are the anticipated currents?  We begin by identifying all power/ground nets shown on the schematic.  To facilitate  recognition of these nets during layout, each net is assigned a color attribute.  If the board is multilayer, and internal distribution planes are to used, planes are created on appropriate layers and assigned to specific nets.  If a plane layer will be used to distribute more that one power or ground net, then the plane is split into separate regions each assigned to a separate net.  The exact size, shape, and location of these regions will be determined during layout.

High Current and High Voltage Nets

Space accommodation must be made in the layout for nets which will carry large currents. For currents beyond a few amperes, trace paths become wide enough to influence the layout of parts.  On external part-mounting layers, wide traces directly interfere with part positioning.  From the point of view of component layout, the area occupied by the trace is subtracted from the total board space available for mounting parts. Wide traces on inner layers may not directly impact part placement, but will interfere with vias normally associated with component footprints. High current paths on inner layers are much wider than they would be on an external layer, given the same current requirement and copper foil thickness. A wide inner-layer path  cannot be perforated with via holes if the rated current capacity is to be maintained.  The external layer above the trace is usable for part mounting, but the part's associated vias will be forced away from the part in order to clear the wide conductor.  There may also be concerns about coupling: Do we really want a switched 15A current flowing directly under a sensitive device?

High voltage nets pose a different set of problems.  Foremost is electric shock hazard, followed by hazards to adjacent circuits.  Safety issues are mitigated by implementing separation/isolation measures.  The air clearance between HV nets and other nets must be wide enough to prevent arcing.  The path distance over adjacent insulation must meet a minimum value (creepage) dependent on voltage and environmental category.  Further measures, if warranted, are physical barriers (cover the exposed HV conductors), placards (print an HV warning in a conspicuous location on the board), and indicators (light a red LED marked "Danger- Lethal High Voltage Present".

Setting Clearance Rules & Trace Widths

By this point, the identity and requirements of all the nets is known well enough to create design rules for each net or class of net. Minimum allowable clearances are specified for each net or class of net.  Minimum and recommended trace widths are specified.  Differential pairs and other special nets are defined.  Hi-speed topology and node order are established.

Setting Via Sizes, Defining Layer Usage

Via sizes are defined based on the layout requirements.  A high-density digital board using .025" pitch components or BGAs may require small .010" via holes to allow routing.  A board using .050" pitch SOICs might use a .015" via.  Higher current nets may need .028" vias.  The via sizes for any board layout are selected to provide interlayer connections without creating significant obstacles to routing, while at the same time meeting the current requirements. Minimum allowable via sizes are dependent on board thickness.  High aspect ratio (small via, thick board) must be avoided.  During board processing, plating solutions have limited ability to wet high aspect vias, resulting in plating voids and unreliable vias.

Layer stackups vary widely from board to board.  In addition to two external layers,  boards may also have a number of internal layers.  For these multilayer designs, an even number of inner layers facilitates a balanced stack-up (mirror-image layer stacks above and below the board thickness center). Boards using balanced stackups are said to be less prone to warp and twist, conditions likely to be troublesome during assembly and soldering operations. 

Layers may be dedicated to trace routing, or as plane layers used for power distribution, shielding, or returns.  It is also common practice to use split-purpose layers containing both traces and plane areas.  Traces may be routed in sections entirely cleared of plane copper, or traces may be embedded, i.e., surrounded conformally by plane copper.  Typical stackups will place power/ground planes in the center of the stack.  Additional routing layers can be added above and below the central planes. For situations requiring a reference/return plane directly under external-layer traces (stripline, microstrip), a four layer board provides the required structure.  If more than four layers are required to route the board, the additional trace layers are placed between the plane layers, thus maintaining the reference planes directly adjacent to the external traces. 

Component Placement

Building The Functional Groups

Using the schematic as a guide, and manufacturer's reference layouts if applicable, each functional group of circuitry is constructed in idealized form, outside the board outline.  This technique provides important benefits over traditional direct-to-board layout. Each group is constructed in "ideal" form, i.e., the component arrangement can be designed to maximize goals without interference from extraneous factors.  Typical goals may be close-in bypass caps, minimized length of Hi-Z nets, uniform component orientations, short connections overall, or simply copying a reference layout.   Where required, copper heatsinks of recommended area are added to devices during this phase.  If the board seems to be a candidate for single-side component mounting, the groups are constructed as such.  If it appears that area constraints or other factors favor a 2-sided component layout, the groups are designed as 2-sided.  An important benefit of this technique is accurate determination of the native shape and size of the idealized groups.  This technique requires no more time than direct-to-board layout.

Fitting Circuit Groups to the Board Area

The second phase of component placement brings all circuit groups onto the board and arranges these groups to achieve sensible signal flow, while also meeting circuit segregation and isolation requirements. 

Placement of groups is driven by the various goals and constraints specific to the board.  For example, where a power input connector is a fixed-location item, and the currents require a sizeable width trace, then the power supply circuits may want to be positioned nearby in order to minimize the trace length.  Similarly, a connector bringing sensitive input signals to preamps suggests placing the preamps near that connector.  As a general rule, fixed-position connectors carrying signals which need short paths will drive the positioning of the  connected circuit groups.  Other factors may intervene:  the switching regulator input filter caps need to be placed tight to the device input pins, but ceiling constraints force the relatively tall filter caps to be located elsewhere, dragging the entire switcher with them!  Layout development is usually a series of compromises. Goals are prioritized, and

When all groups needing short connections to fixed components have found positions on the board, the remaining circuit groups are shuffled (still off-board) into a signal-flow arrangement which approximates the shape of the available area. In situations where the ideal flow cannot be met within the available shape, the best possible arrangement is found to minimize connection lengths and cross-overs.  Analog/digital or other segregation criteria are implemented now by defining separate regions. The arrangement of groups now constitutes a floorplan based on actual circuitry, and will represent the area and shape of circuit groups much more accurately than typical pre-layout floorplans based on wishful thinking.   At this point a determination is made about potential fit.  The available area is either sufficient, marginal, or hopeless.  When the area looks to be insufficient,  the layout approach is modified, provided some viable options exist.  For example, if a single-sided layout proves unlikely, the approach can be changed to utilize both sides of the board.

Groups are now moved onto the board one by one, maintaining the floorplan arrangement.  For boards with more-than-ample space and no inconvenient obstacles, the groups will drop in easily without interference.  Unfortunately, this almost never happens.  Real-world boards must usually be made as small as possible, and full product functionality invariably requires more circuitry than will comfortably fit.  The shape of available area will seldom be ideal, and immovable items like mounting holes can sometimes be in the most obstructive positions imaginable.  Due to these realities, the shape of groups must be individually adjusted to fit the available space.

The Art of Morphing

On a typical board, the various circuit groups are not all of the same size or shape.  Rarely do groups take the form of regular polygons which can be stacked like bricks.  Due to these irregular shapes,  idealized groups placed adjacent to each other will leave significant unused board space between. Reshaping of groups to reduce unused space makes the most effective use of the available area. The process of reshaping circuit blocks to improve physical fit, while retaining the performance values built into the idealized group, is called "morphing".

Circuit groups which are built in ideal configuration can always be modified to occupy a differently-shaped area to allow or improve fit on the board.  Modifications to ideal groups may be entirely benign or may have functional consequences, depending on the change.  Consequently, group morphing is done using a two-tiered approach.  Each part within a group contains rules which define its relationship to other parts.  For example, bypass caps have a minimum distance rule to particular power pins.  The input resistors attached to an op-amp have a minimum distance rule to the input pin and a minimum spacing rule to output nets.  These components can be shifted, but the options are limited if rules are to met.  On the other hand, many components have only connectivity rules (as defined by the netlist connections), and therefore more freedom of movement.   For example, a pair of resistors forming a low-Z voltage divider at an op-amp input can go anywhere.  Series components in low-Z outputs need not be parked directly at a device output pin.  The art of morphing the shape of functional groups requires knowledge of the rules, the ability to recognize alternate configurations which also meet the rules, and a clear understanding of which parts can be repositioned without consequences.  The process of adding groups to the board and fitting them together proceeds until completed.  During this phase, space accommodation is made for high-current paths, high-voltage nets, and isolation barriers.

Positioning MarkingText

During the building of the circuit groups, reference designators are positioned adjacent to each component. Reference designators will appear on the board silkscreens and the text characters must be large enough to be legible.  Silkscreen ink must also remain completely off solder lands.  As circuit groups are morphed into final positions, we try to keep up with relocating reference designators as needed.  A final final checking pass is usually necessary to catch any that were missed. . 

Once the reference designators are positioned, then the board part number, assembly part number, and revision codes are positioned.  By default, we place the board part number with revision code on the secondary side etch layer (in copper text), and the assembly number with revision code is placed in primary-side silkscreen ink.  An alternate format replaces the assembly revision code with an inked rectangle, on which a code may be stamped or written during manufacture.

First Checkplots Review & Placement Adjustments

With the initial placement finished, we release checkplots showing the top and bottom views of the board.  Accompanying the checkplots are comments and questions from the layout designer.  Checkplots provide an opportunity for the engineer to review and comment on the layout before we proceed further.  Provided the layout meets the ordered specification, we expect no major changes, but engineering review often suggests worthwhile improvements.  Upon receiving the engineer's comments, we install all ordered changes and with that, the component placement phase is complete. 

Designing the Conductor Pattern

Power & Ground Distribution Using Traces

On most boards, the power and ground nets are among the first to be routed.  If the design is a two-layer stackup, the power and ground nets are almost always routed as traces.  Common practice is to establish wide Lo-Z feeder trunks extending from the power source to the farthest load point.  Branches from the trunk then feed individual loads along the way.  The voltage source and return are connector pins in most cases.  In some cases, voltages are distributed directly from this connector.  Alternately the connector feeds one or more on-board regulators or converters, and these circuits then deliver power to the remaining circuits.  In either case, careful attention must be given to the location of input/output capacitors.  While the location of bulk input capacitance is seldom particularly critical, it is common practice to place the bulk caps near the input connector.  Where regulator devices are used, the location of input and output caps is usually specified by the device manufacturer to be as close as possible to the device pins.

Power & Ground Distribution Using Planes

Multilayer boards allow the use of dedicated plane layers for the distribution of power and ground.  Planes can provide very low impedance paths, and the intrinsic capacitance between closely-spaced plane layers can be functionally significant.  In addition, removing the power distribution from the trace layers allows more space for signal traces.  A plane layer can distribute a single power or ground throughout the entire board, or a layer may distribute multiple powers by splitting the layer into several regions isolated by clearance lines.  Plane areas are connected to sources and loads using through-hole pins or via holes, from an external layer.  Vias must be sized appropriately for the currents, and where a single via is insufficient, multiple vias must be used.   Ground return connections to the plane are made by installing vias and short traces at all grounded device pins or lands.

Bypass/Decoupling Caps

When planes are used to distribute powers and grounds, we typically install a via and a short connecting trace to supply power to the load device bypass cap. A short trace from the cap then supplies power to the device. The location of individual device bypass caps was established when the circuit groups were built, and provisions were made at that time for sufficient space for the necessary vias. 

Routing Critical Signals

Our definition of "critical signal" is any net requiring special attention.  We install critical signals early to provide the widest scope of routing options. A set of high-current DC paths may need considerable space, and are best installed while the space and options are available. Other nets require control of topology (branching), geometry, location, or other attributes critical to circuit performance.   Controlled-impedance nets are a class of critical signal.  High-speed nets are classed as critical signals, as are differential pairs regardless of speed.  Where crosstalk must be minimized, coupling must be controlled.  Once the critical signal paths have been installed and tweaked to perfection, they are locked down to prevent inadvertent changes.

Routing Non-Critical Signals

Remaining signals are routed in a prioritized sequence.  The internal connections of Individual circuit groups are routed first, followed by  group interconnections.  Clocks, hi-z nodes, and other sensitive nets are given priority.  Provided the available space is sufficient, and the component placement matches the signal flow, routing of non-critical nets usually proceeds quickly.  High-end interactive tools relieve the layout designer of the "busy work" of full-manual routing and yield high-quality routing completion of low-risk nets in a fraction of the time. 

Gate and Pin Swaps

Routing in congested areas can often be eased by re-assigning or "swapping" equivalent units of multi-unit devices.   Logic gates, op-amps, and resistor networks are typical candidate devices.  Further optimization is possible by re-assigning equivalent pins, for example the inputs of a 2-input gate.  Pin swapping is very useful when routing resistor networks, and can sometimes be applied to connectors provided the pin assignments are not fixed.  While swaps do smooth the flow of routing considerably, all swap operations must flow back to the netlist and schematic to maintain tracking. We provide a back-annotation file for this purpose.

Test Access

For boards needing 100% test access for automated testers, one or more test pads are added to each net during routing.  A single test pad is normally sufficient for signal nets, but in order for the tester to source/sink larger currents, selected power/ground nets (and occasionally other nets) are often provided with multiple test pads.  A typical test pad is a .035" diameter drilled via pad, the hole being .015" diameter.  Test pads can also be non-drilled in some applications. Test pads are usually arranged to be probed from one side of the board, although some board designs may require access from both sides.  Test points must be positioned on a uniform coordinate grid referenced to an established datum, such as a fiducial target.  In order to test the board, a test fixture must be built having test probes and guide posts which match the test points and guide holes on the circuit board.  The cost of test fixtures increases as the grid increment decreases.  At one time, a test grid increment of .100" was widely used, but smaller component package sizes and the resulting increase in board density has made the .100" grid unusable for typical surface-mounted designs.  A grid of .050" is now popular, usable for all but the most difficult situations.

Layout Checking

When routing is complete, the layout is thoroughly checked for compliance with physical design rules. This check ensures that electrical clearances, conductor widths, and high-speed rules are implemented as originally planned.  This is not the first round of checking.  DRC is performed throughout the placement and routing process, either continuously using a warn/prevent monitor, or by periodic manual calls to the checker.  A different check compares the layout connectivity to the original netlist.  This check will confirm that the parts and connections have not been modified inadvertently.

Second Checkplots Release

With all routing completed and the layout thoroughly checked, checkplots are ready to be released for engineering review of all circuit layers and silkscreens. In order to include the fabrication drawing and assembly drawing for review, final drawing details are completed, and the package of checkplots and drawings is released.

Documentation Drawings

The standard drawings required for circuit board manufacturing are the board fabrication drawing (sometimes called a drill drawing), and the board assembly drawing.  These drawings provide detailed specifications related to the manufacture of the bare board and to the finished electronic assembly.  By the time the board layout is complete, the graphical elements of these drawings and many of the required notes already exist.  Only final details and minor adjustments need be added to complete these drawings. 

Fabrication (Drill) Drawing

The fabrication drawing is composed of 6 basic elements- the title block, the board outline, the drill pattern, the drill table, the layer stackup, and the manufacturing notes.  Additional views may be added to detail specific board features when necessary.

The title block contains all information related to the identification of the board, the drawing's origin and sign-off history, the current revision code and a revision history, the drawing size and scale, the measurement units, the default tolerances, drawing owner name, and proprietary rights notices.

The main graphical feature of the fab drawing is a dimensioned board outline enclosing a pattern of symbols which represent the location of drilled holes.  The outline dimensions specify the envelope profile to the manufacturer.  Typically, the location of several holes in the pattern are dimensioned to a board corner.  These may be mounting holes or dedicated "tooling" holes to be used for processing alignments.  These dimensions serve to "tie" the board outline to the drill pattern.

Hole sizes are indicated by unique symbols. These symbols are listed in a drill table showing hole size, plating status, and size tolerance.  It is important to understand that the drill drawing is not a drilling template. The board outline and drill symbols image is not used directly in the drilling process.  Boards are drilled by automated high-speed machines driven by a drill program file provided by the layout department for this purpose.

A layer stackup graphic provides a cross sectional view of the board.  This graphic shows all copper layers and intervening dielectric layers.  Also specified are the initial and final (post-plating) copper thicknesses, the board thickness and tolerance, and the type laminate material to be used.  Where dielectric thickness must be controlled, these thicknesses are specified. 

Manufacturing notes will vary according to specific requirements, however all boards require specification of key process steps.  At minimum, the fab notes must specify the laminate material, the surface finish, the soldermask type and color, and the silkscreen color.  Additional notes should specify manufacturing standards, drawing interpretation standards, the positional tolerance of drilled holes, minimum plating thickness in holes, and the location of the manufacturer's ID and production date markings.

Assembly Drawing

The assembly drawing is composed of 3 basic elements- the title block, the component side image(s), and the assembly notes.  As on the fab drawing, additional views may be added to detail specific board features when necessary. 

The assembly drawing contains a separate image for each side of the board to be assembled.  These images depict the component bodies as they appear on the board silkscreen, and typically the component solder lands are shown rather than the actual component pins.  Each part is identified by a reference designator, and critical orientations are indicated by polarity markings and text items.  This level of board representation is fully sufficient for accurate assembly, is easy to produce at relatively low cost, and therefore is widely used.  For purposes requiring a more detailed view (e.g., product manuals, or per customer requirements), detailed component models can be substituted to create a publication-quality drawing.

Assembly notes vary widely, depending on the board.  At minimum, notes must specify the applicable assembly/inspection standards and performance class, and should indicate that ESD precautions are required.  Additional notes are required to specify parts requiring special handling, the location of press-on labels, special marking requirements, type of conformal coatings, and compliance with RoHS and other materials directives.

Final Adjustments

Engineering review can be expected to yield at least a few corrections, questions, and changes.  The layout and drawings are updated as ordered and the review package is re-released to obtain approvals.  When approved by engineering, the layout enters the output phase of work.

Final Checking

If final adjustments were made to the layout, then both DRC and netlist checking must be repeated to ensure that any hidden problems are scrubbed out of the layout.  The layout will not enter the output phase until the database is certified clean and signed-off by the layout designer.

Generating Outputs

The manufacture of electronic assemblies uses a well-standardized set of files and documents. The number and types of files required varies depending on the type of board construction.

Gerber Artworks

The circuit layers, silkscreens, and soldermasks are provided as gerber-format files unless otherwise requested. While alternate formats are available for data transfer to manufacturing (for example ODB++), the gerber file format remains dominant in the industry.  For each circuit layer, a separate gerber artwork file is generated, using the following file parameters.

• Units: English
• Leading digits: 3
• Trailing Digits: 5
• Zero suppress: Leading
• Format: RS-274X
• Coordinates: Absolute
• Repeat suppress: Yes

Additional gerber files are provided for silkscreens, soldermasks, and for solder pastemasks.  All gerber files share a common origin point for automatic alignment in gerber viewers.

Machine Drive Files

During board manufacture, holes are drilled by automated high-speed  drilling machines.  We provide the drill program file to drive these machines.  The drill file lists the size and location of each hole. Examination of a drill file will reveal that the hole sizes specified are larger than the nominal finished hole size as specified on the drill drawing.  This oversize compensates for the copper thickness added to holes to create a conductive path.  Drilling holes at the nominal size without this pre-compensation can result in holes plated to a size smaller than the toleranced minimum.

Except for small-quantity builds where hand-assembly is done, boards are assembled by machine.  By using machine vision to locate the fiducial targets, pick-and-place machines position parts quickly and accurately. We provide the pick-and-place drive file which defines the position, orientation, and device type for each part to be mounted. 

For boards which are set-up for automated testing, an IPC-356 netlist file is provided, along with a report of all testpoints indexed by net name and x,y location. 

Packaging and Shipping

Output files are packaged together in a zipped container.  We retain a copy in our archives, and send a copy to the customer via email.  Contents of our standard delivery include:

• artwork gerbers
• fab drawing & drill files
• assembly drawing & bom
• centroids file
• test files
• CAD database files
• schematic & netlist
• board outline drawing
• layout instructions

The schematic, outline drawing, and instructions are for archival purposes only. These files are not needed for board manufacturing, and you may not want to distribute these source files.  We recommend that customers archive the full file, make a copy, remove selected files from the copy, then release this copy to manufacturing.

 

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